?1 cxk5v8257btm/bym/bm -70ll/10ll e93836a5z-st 32768-word 8-bit high speed cmos static ram description the cxk5v8257btm/bym/bm is 262,144 bits high speed cmos static ram organized as 32768- words by 8 bits. a polysilicon tft cell technology realized extermely low stand-by current and higher data retention stability. operating on a single 3.3v supply, directly lvttl compatible (all inputs and outputs). and special feature are, low power consumption, high speed and broad package line-up. the cxk5v8257btm/bym/bm is a suitable ram for portable equipment with battery back up. features single +3.3v supply: 3.3v 0.3v directly lvttl compatible: all inputs and outputs fast access time: (access time) cxk5v8257btm/bym/bm -70ll 70ns (max.) -10ll 100ns (max.) low standby current: cxk5v8257btm/bym/bm -70ll/10ll 3.5 a (max.) low power data retention: 2.0v (min.) available in many packages cxk5v8257btm/bym 8mm 13.4mm 28 pin tsop package cxk5v8257bm 450mil 28 pin sop package function 32768-word 8 bit static ram structure silicon gate cmos ic block diagram sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxk5v8257btm 28 pin tsop (plastic) cxk5v8257bym 28 pin tsop (plastic) cxk5v8257bm 28 pin sop (plastic) memory matrix 512 512 i /o gate column decoder row decoder buffer buffer buffer i /o buffer v cc gnd i /o1 i /o8 a14 a13 a12 a11 a9 a8 a7 a6 a5 oe we ce a4 a10 a3 a2 a1 a0
?2 cxk5v8257btm/bym/bm pin configuration (top view) pin description oe a11 a9 a8 a13 we vcc a14 a12 a7 a6 a5 a4 a3 a10 ce i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 cxk5v8257btm (standard pinout) a3 a4 a5 a6 a7 a12 a14 vcc we a13 a8 a9 a11 oe a2 a1 a0 i/o1 i/o2 i/o3 gnd i/o4 i/o5 i/o6 i/o7 i/o8 ce a10 cxk5v8257bym (mirror image pinout) 7 6 5 4 3 2 1 28 27 26 25 24 23 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 19 18 17 16 15 20 21 22 23 24 25 26 27 28 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 gnd cxk5v8257bm 16 9 8 21 20 19 18 17 10 11 12 13 14 15 a a vcc we a13 a8 a9 a11 oe a10 ce i/o8 i/o7 i/o6 i/o5 i/o4 address input data input/output chip enable input write enable input output enable input +3.3v power supply ground a0 to a14 i/o1 to i/o8 ce we oe v cc gnd symbol description supply voltage input voltage input and output voltage allowable power dissipation operating temperature storage temperature soldering temperature ?time v cc v in v i/o p d topr tstg tsolder ?.5 to +4.6 ?.5 * 1 to v cc + 0.5 ?.5 * 1 to v cc + 0.5 0.7 0 to +70 ?5 to +150 235 ?10 v v v w ? ? ? ?s item symbol rating unit h l l l h l h h l not selected output disable read write high z high z data out data in i sb1 , i sb2 i cc1 , i cc2 i cc1 , i cc2 i cc1 , i cc2 ce oe we mode i/o1 to i/o8 v cc current absolute maximum ratings (ta = 25?, gnd = 0v) * 1 v in , v i/o = ?.0v min. for pulse width less than 50ns. truth table : ??or ? dc recommended operating conditions (ta = 0 to +70?, gnd = 0v) supply voltage input high voltage input low voltage v cc v ih v il 3.0 2.0 ?.3 * 2 3.3 3.6 v cc + 0.3 0.8 v item symbol min. typ. max. unit * 2 v il = ?.0v min. for pulse width less than 50ns.
?3 cxk5v8257btm/bym/bm input pulse high level input pulse low level input rise time input fall time input and output reference level -70ll -10ll v ih = 2.0v v il = 0.8v t r = 5ns t f = 5ns 1.4v c l * 2 = 30pf, 1ttl c l * 2 = 100pf, 1ttl item conditions ttl c l output load conditions ac characteristics ac test conditions (v cc = 3.3v 0.3v, ta = 0 to +70?) * 2 c l includes scope and jig capacitances. i/o capacitance (ta = 25?, f = 1mhz) input capacitance i/o capacitance item symbol test condition min. typ. max. unit c in c i/o v in = 0v v i/o = 0v 8 10 pf pf note) this parameter is sampled and is not 100% tested. electrical characteristics dc characteristics (v cc = 3.3v 0.3v, gnd = 0v, ta = 0 to +70?) item symbol test conditions min. typ. * 1 max. unit input leakage current output leakage current operating power supply current average operating current standby current output high voltage output low voltage i li i lo i cc1 i cc2 i sb1 i sb2 v oh v ol vin = gnd to vcc ce = v ih , oe = v ih or we = v il , v i/o = gnd to v cc ce = v il , v in = v ih or v il , i out = 0ma min. cycle, duty = 100%, i out = 0ma ce 3 v cc ?0.2v ce = v ih i oh = ?ma i ol = 2.0ma ?.5 ?.5 2.4 0.5 0.5 2 40 35 3.5 0.7 0.35 0.7 0.4 0.9 21 18 0.12 0.06 ? ? ma ma ? ma v v * 1 v cc = 3.3v, ta = 25? 70ll 10ll 0 to +70? 0 to +40? +25?
?4 cxk5v8257btm/bym/bm -70ll -10ll item symbol unit min. max. min. max. -70ll -10ll item symbol unit min. max. min. max. t rc t aa t co t oe t oh t lz t olz t hz * 1 t ohz * 1 70 20 10 5 70 70 35 30 30 100 20 10 10 100 100 50 35 35 ns ns ns ns ns ns ns ns ns read cycle time address access time chip enable access time (ce) output enable to output valid output hold from address change chip enable to output in low z (ce) output enable to output in low z (oe) chip disable to output in high z (ce) output disable to output in high z (oe) t wc t aw t cw t dw t dh t wp t as t wr t wr1 t ow t whz * 2 70 60 60 30 0 55 0 0 0 10 30 100 80 80 35 0 60 0 0 0 10 35 ns ns ns ns ns ns ns ns ns ns ns write cycle time address valid to end of write chip enable to end of write data to write time overlap data hold from write time write pulse width address setup time write recovery time (we) write recovery time (ce) output active from end of write write to output in high z read cycle (we = ?? * 1 t hz and t ohz are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. write cycle * 2 t whz is defined as the time required for outputs to turn to high impedance state and is not referred to as output voltage level.
?5 cxk5v8257btm/bym/bm address t aa t rc t oh data out previous data valid data valid address t aa t rc t co t lz t hz t ohz t oe t olz ce oe data out high impedance data valid address t aw t wc t cw t as t wp t dh t whz t dw ce we data out high impedance data valid t ow ( * 2 )( * 2 ) oe data in t wr ( * 1 ) timing waveform read cycle (1): ce = oe = v il , we = v ih read cycle (2): we = v ih write cycle (1): we control
?6 cxk5v8257btm/bym/bm address oe t wc t aw data valid t as t cw t wr1 t wp t dw t dh high impedance ce we data out data in ( * 3 ) write cycle (2): ce control * 1 write is executed when both ce and we are at low simultaneously. * 2 do not apply the data input voltage of the opposite phase to the output while i/o pin is in output condition. * 3 t wr1 is measured at the period from the rising edge of ce to the end of write cycle.
?7 cxk5v8257btm/bym/bm v cc 3.0v 2.0v v dr ce gnd t cdrs data retention mode t r ce 3 v cc ? 0.2v data retention waveform low supply voltage data retention waveform data retention characteristics (ta = 0 to +70?) item symbol test condiitions min. typ. max. unit data retention voltage data retention current data retention setup time recovery time v dr i ccdr1 i ccdr2 t cdrs t r ce 3 v cc ?0.2v v cc = 3.0v, ce 3 2.8v v cc = 2.0 to 3.6v, ce 3 v cc ?0.2v chip disable to data retention mode 2.0 0 5 3.6 3 0.6 0.3 3.5 0.1 0.12 * 1 v ? ? ns ms 0 to +70? 0 to +40? +25? * 1 v cc = 3.3v, ta = 25?
?8 cxk5v8257btm/bym/bm package outline unit: mm cxk5v8257btm sony code eiaj code jedec code package structure package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy 28pin tsop (plastic) * 8.0 0.1 0.55 0.1 * 11.8 0.1 13.4 0.3 1.2 max 0.5 0.1 0?to 10 0.2 ?0.05 + 0.1 0.05 ?0.05 + 0.1 0.127 ?0.02 + 0.07 a 7 1 28 22 8 21 tsop-28p-l01 tsop028-p-0000-a 0.1 detail a 0.2g note: dimension * ?does not include mold protrusion. sony code eiaj code jedec code package structure package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy 28pin tsop (plastic) * 8.0 0.1 0.55 0.1 * 11.8 0.1 13.4 0.3 1.2 max 0.5 0.1 0.2 ?0.05 + 0.1 0.05 ?0.05 + 0.1 0.127 ?0.02 + 0.07 a 22 28 1 7 21 8 tsop-28p-l01r tsop028-p-0000-b 0.1 0?to 10 detail a 0.2g note: dimension * ?does not include mold protrusion. cxk5v8257bym
?9 cxk5v8257btm/bym/bm sony code eiaj code jedec code package structure package material lead treatment lead material package weight epoxy resin solder plating 42 alloy 28pin sop (plastic) sop-28p-l05 * sop028-p-0450 0.7g m 18.0 ?0.1 + 0.4 0.4 0.1 1.27 8.4 ?0.1 + 0.3 11.8 0.4 0?to 10 0.15 ?0.05 + 0.1 1.0 0.2 0.1 ?0.05 + 0.2 0.15 2.3 ?0.15 + 0.4 15 14 1 28 0.24 cxk5v8257bm
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